Conventionally, a large number of identical semiconductor devices are formed on a common silicon wafer by selectively subjecting the wafer to a sequence of processing steps. The wafer is then scored and diced to separate the individual semiconductor devices called chips. Solder preforms are used to bond connection leads to opposite major surfaces of a chip to form a semiconductor device such as a diode.
FIG. 1 is a partial cross section of a typical planar diode semiconductor device formed on a semiconductor substrate. The diode comprises a layered substrate including N.sup.+ -type lower layer 1 and N-type upper layer 2 formed immediately thereon. The diode is a planar type device comprising stacked layers of semiconductor material. P-type region 3 is formed by diffusing P-type impurities into N-type upper layer 2 through an aperture in silicon oxide layer 4 formed on upper layer 2.
An upper metallization layer 5 is formed on an upper surface of P-type region 3 and a lower metallization layer 6 is formed on an exposed lower surface of lower layer 1. Lower metallization extends across the entire lower surface of the substrate. However, upper metallization layer 5 must be patterned so as not to extend beyond the borders of each diode. This is because metal formed in the vicinity of dicing lines defining the individual devices can produce residual metal particles during dicing operations. The residual metal particles can cause lateral shorting between metallization layer 5 and underlying upper layer 2 thereby providing a low resistance path around the PN junction and rendering the diode inoperative. Extending metallization layer 5 to the edge of the chip results in lateral passivation problems normally encountered with mesa-type diodes.
Conventionally, upper and lower metallization layers 5 and 6 are formed by depositing successive metals on the surfaces of a substrate by successive evaporation or sputtering steps. Typically, an aluminum layer is formed directly on the substrate with successive layers of nickel and gold formed thereon. The nickel layer is essential to permit attachment of a conductor by welding. The underlying aluminum layer is used to prevent migration of the overlying nickel into the substrate and because the aluminum provides a low resistance electrical contact with the substrate. The uppermost gold layer prevents oxidation of the nickel layer prior to the welding phase.
After the entire upper and lower surfaces of the substrate are covered by the aluminum/nickel/gold layers, the upper layer is patterned by photoetching to form separate metallization layers 5 constituting individual bonding pads. Device leads are attached to the bonding pads using solder preforms.
A disadvantage of the conventional photoetching technique of forming the bonding pads is that a substantial portion of the upper metallization layer, typically ranging from 40 to 50%, must be removed by etching. As described, this layer comprises a relatively expensive noble metal such as gold which is not easily recoverable from an etching solution and is therefore wasted.
To avoid the above-mentioned metal wasting, a method is disclosed in the Patent Abstract of Japan, Vol. 11, No. 33, JP 61-202429, of forming a metal contact on a surface of a semiconductor chip comprising a diffused region delimited by an isolating layer forming a mask. The method comprises the steps of forming a polysilicon layer doped to be the same conductivity type as the diffused region, patterning the polysilicon layer so that it covers the diffused region and overlaps the internal peripheral surfaces of said mask, and immersing the wafer in a metal plating bath so that metal is deposited on the conductive surfaces of the wafer.
It appears that the components produced according to this method have a relatively short lifetime and that their characteristics tend to vary over time.